The ball grid array (BGA) is a well-known type of surface-mount package that utilizes an array of metallic bumps or nodules, often denominated “solder balls,” as means for providing external electrical connections. The solder balls are attached to a laminated substrate at the bottom side of the package. The die, or integrated circuit (IC) chip of the BGA is commonly connected to the substrate by flip-chip connections. The term “flip-chip” refers to a semiconductor chip that can be mounted directly onto a substrate or PCB in a “face-down” orientation. Electrical connections are completed through conductive bumps built on the surface of the chip, thus the mounting process is frontside down. Because flip-chips do not require wirebonds, they can be made smaller than their conventional counterparts and can avoid performance problems related to inductance and capacitance associated with bond wires. The space between the flip-chip surface and the PCB or substrate is typically filled with a non-conductive adhesive underfill material to protect the contacts and the flip-chip surface from moisture, contaminants, and other hazards. The underfill material also mechanically locks the flip-chip surface to the board or substrate.
The layered substrate of a BGA has internal conductive paths that electrically connect the chip bonds to the ball array. Often, the BGA substrate is formed with a structure termed a “ground ring” on its surface, though it is most often rectangular. The ground ring is an electrically conductive trace, usually metal or alloy, arranged to encircle the chip and is used to connect the ground pads of the packaged chip to ground lines of the PCB. The ground ring is separated from the chip attachment site by a concentric non-conductive gap on the substrate surface.
An advantage of the flip-chip BGA is its high interconnection density, i.e., the number of balls per given package volume is high. All packages have drawbacks, however. The high density of the flip-chip BGA which makes it desirable for many applications can lead to a concentration of excess heat generated during operation of the circuitry. In general, the semiconductor chip generates heat when operated and cools when inactive. Due to the changes in temperature, the package as a whole tends to thermally expand and contract. However, since in many cases the thermal expansion behavior of the packaged device, its internal components, and PCB differ, stresses can occur at the connecting solder balls, within the PCB or chip, or at the junctions of the package components.
In general, the excess heat making its departure from a BGA package may be understood in terms of following three thermal paths. A fairly direct thermal path exists from the front surface of the chip though the underlying substrate, however heat transmission is impaired by the generally poor thermal properties of the substrate itself. This thermal path is sometimes improved by the addition of thermal vias or thermal BGA balls designed to increase heat conduction away from the chip and substrate respectively, but problems remain, particularly in the case of silicon on insulator (SOI) devices. SOI is a semiconductor wafer technology that produces higher-performance, lower-power devices than conventional CMOS techniques. SOI uses a thin insulating layer, such as silicon oxide or glass, between a thin layer of silicon and the silicon substrate. This process helps reduce the amount of electrical charge required to operate the chip, making it faster and more energy-efficient. Although SOI devices typically generate less heat than other types of devices, ridding the SOI devices of excess heat is still a consideration, and the insulating layer is generally unhelpful in this regard. The differences between the coefficients of thermal expansion of the silicon and oxide, glass, or other insulating layer(s) can result in stresses within the silicon layer(s), which tend to diminish electrical performance. Additionally, stresses among and between the layers can cause mechanical separation leading to device failure.
Following a second thermal path, heat may also travel in the plane of the substrate. This can be a fairly good thermal path, particularly in packages with thick substrates, but is generally longer and in some instances may be insufficient to adequately dissipate heat generated by the IC. The third thermal path, from the backside of the chip to the outside of the package, is typically a relatively poor thermal path due to the inherent heat resistance of the surrounding encapsulant material, although heat conduction may sometimes be improved by the use of heat-conductive mold compound material, or the inclusion of a heat spreader or external heat sink. Current thermally enhanced flip-chip BGAs do not allow for electrical contact to the backside of the die. Contact to the backside of the die is important for SOI processes in order to facilitate AC operation and stability. Improvements to heat dissipation in BGA packages are necessarily limited by the geometry of the BGA and are not sufficient in all cases, leaving a need for further improvements in thermally enhanced BGA packages. Additionally, it is desirable to provide for electrical contact to the backside of the chip, particularly in SOI devices.
Due to these and other problems, it would be useful and advantageous to provide surface-mountable semiconductor packages such as flip-chip BGA packages with improved thermal conduction properties and/or improved back-side grounding, and to provide methods for manufacturing such packages.